1. Field of the Invention
The present invention relates to a semiconductor memory device and, particularly, to a semiconductor memory device comprising a plurality of memory macros.
2. Description of Related Art
Normally, electronic devices such as computers include data storage means for storing data. SRAM (Static Random Access Memory) is one of semiconductor memory devices which are used as the data storage means. SRAM has advantages in terms of high-speed operation, e.g., it does not require a refresh operation, and access time taken for access to a memory cell is short.
Japanese Unexamined Patent Publication No. Hei 7 (1995)-254284 discloses a technology relating to a semiconductor memory device which enables high-speed write and read operations and can reduce power consumption during an inactive state. FIG. 5 is a block diagram depicting the semiconductor memory device pertaining to Japanese Unexamined Patent Publication No. Hei 7 (1995)-254284. The semiconductor memory device shown in FIG. 5 comprises a memory cell array 101, a memory peripheral circuit 102, a power supply line 103 coupled to a power supply voltage VCC, a pseudo power supply line 131 of the memory peripheral circuit 102, a ground line 104, memory cells 105, word lines WL, and bit lines BL. The pseudo power supply line 131 is coupled to the power supply line 103 via a switch SW1.
The memory peripheral circuit 102 is comprised of MOS transistors having a low threshold voltage to implement high-speed data read and write operations. The power supply voltage VCC is supplied through divergent paths to the memory cell array 101 and the memory peripheral circuit 102. The power supply voltage is always supplied to the memory cell array 101 through the power supply line 103 to retain data stored in cells. On the other hand, in the path to the memory peripheral circuit 102, a switch SW1 is provided between the power supply line 103 and the pseudo power supply line 131 which is a power supply line internal to the memory peripheral circuit 102. By controlling this switch to be on, the power supply voltage VCC is supplied to the memory peripheral circuit 102 and the semiconductor memory device turns from an inactive state to an active state, enabling data write and read operations.
When the semiconductor memory device is in the active state, the switch SW1 is on and the power supply voltage VCC is supplied to the memory peripheral circuit 102 and high-speed write and read are performed by the memory peripheral circuit 102 comprised of MOS transistors. When in the inactive state, the switch SW1 is off, thereby stopping the supply of the power supply voltage VCC to the memory peripheral circuit 102 and inhibiting power consumption of the memory peripheral circuit 102. In this way, in the semiconductor memory device pertaining to Japanese Unexamined Patent Publication No. Hei 7 (1995)-254284, by making the switch SW1 remain off when the semiconductor memory device is in the inactive state, it is possible to stop the power supply to the memory peripheral circuit 102. Thus, the power consumption of the semiconductor memory device can be suppressed.
Generally, in a semiconductor memory device using a CMOS integrated circuit, increasing the circuit size results in an increase in parasitic capacitance of an internal power supply line of the semiconductor memory device. For example, consider a case where a switch MOSFET is provided between the power supply line for supplying an external power supply to the semiconductor memory device and the internal power supply line of the semiconductor memory device and power supply to the semiconductor memory device is controlled by means of the switch MOSFET. If the circuit size increases, the parasitic capacitance of the internal power supply line increases and, in consequence, when the switch MOSFET is turned on, a large current (hereinafter, referred to as an inrush current) will flow through it. This inrush current comprises a current needed to charge up a large gate capacitance of the switch MOSFET and a current to charge up the parasitic capacitance of the internal power supply line through a source-drain path of the switch MOSFET. This inrush current increases with an increase in the size of the CMOS circuit like the one mentioned above.
Such inrush current raises a peak current value of the semiconductor memory device and the current capacity of a power supply device to be installed in the system must be large enough to accommodate the peak current value. Even for the semiconductor memory device, the occurrence of such inrush current introduces a large noise in the power supply line, which deteriorates its operation margin.
Japanese Unexamined Patent Publication No. Hei 9 (1997)-231756 discloses a technology relating to a semiconductor memory device which can solve the above-noted problem. The semiconductor memory device disclosed in Japanese Unexamined Patent Publication No. Hei 9 (1997)-231756 comprises a power supply line carrying an operating voltage VCC supplied from an external terminal, a plurality of circuit blocks, each adapted to perform a circuit operation by an operation control signal, internal power supply lines, each provided for each of the circuit blocks, switches MOSFET, each provided between the power supply line and each of the internal power supply lines of the circuit blocks, and a power supply switch circuit adapted to control switching of each of the switches MOSFET by using the operation control signal. Sequentially delayed operation control signals are applied to the gates of the switches MOSFET respectively provided for the circuit blocks. Thus, on-off switching of each of these switches is controlled to occur at different timing.
The semiconductor memory device disclosed in Japanese Unexamined Patent Publication No. Hei 9 (1997)-231756 is configured to shift the timing to turn on each of the switches MOSFET respectively provided for the circuit blocks. Accordingly, an inrush current occurs at different times and, thus, the peak current value can be reduced, as compared with a case where the circuit blocks are activated simultaneously.